EP 0880124 A1 19981125 - Power output stage for driving the cells of a plasma panel
Title (en)
Power output stage for driving the cells of a plasma panel
Title (de)
Leistungsendstufe zum Antreiben von Zellen einer Plasmaanzeigetafel
Title (fr)
Etage de sortie de puissance pour la commande de cellules d'écran à plasma
Publication
Application
Priority
FR 9706498 A 19970522
Abstract (en)
The power output stage (30) includes an input (32) receiving a low voltage input logic signal (IN2) and an output (34) supplying a high voltage control signal (OUT2). An output circuit (36) includes a charge transistor, which receives a high voltage potential(VPP) on a drain and has a source connected to an output (34). The output circuit also has a discharge transistor (40) which receives a reference potential (GND) on a source and has a drain connected to the output (34). A control circuit (42,44,46,52,58) supplies control signals (PCDE,NCDE) to the charge and discharge transistors as a function of the input logic signal. The charge and discharge transistors are of the n-channel VDMOS type. The charge transistor (38) is arranged to form a transistor of composite type P. The control circuit is arranged so that the potential at the grid of the charge transistor falls faster than the potential at the output when the input logic signal controls a discharge of the output .
Abstract (fr)
L'invention concerne un étage de sortie de puissance (30) pour la commande de cellules d'écran à plasma. Il comprend deux transistors de charge et de décharge (38, 40) de type VDMOS à canal N, le transistor de charge étant agencé de sorte à former un transistor de type P composite. Ces transistors permettent de fournir un courant de charge à une sortie (34) et d'absorber un courant de décharge provenant de cette sortie. Deux inverseurs (46, 52) sont dimensionnés de sorte que le potentiel de la grille de commande du transistor de charge (38) chute plus rapidement que le potentiel de la sortie lorsque l'on commande une décharge de cette sortie. On réalise, ainsi, un étage de sortie d'encombrement limité et sans risque de conduction simultanée des transistors de charge et de décharge. <IMAGE>
IPC 1-7
IPC 8 full level
G09G 3/20 (2006.01); G09G 3/26 (2006.01); G09G 3/28 (2006.01); G09G 3/288 (2006.01)
CPC (source: EP US)
G09G 3/26 (2013.01 - EP US); G09G 3/296 (2013.01 - EP US)
Citation (search report)
- [A] GB 2291549 A 19960124 - MICRON TECHNOLOGY INC [US]
- [A] EP 0351820 A2 19900124 - TOSHIBA KK [JP]
- [A] DE 3730649 A1 19890330 - SIEMENS AG [DE]
- [A] PATENT ABSTRACTS OF JAPAN vol. 15, no. 4 (E - 1031) 8 February 1991 (1991-02-08)
- [A] L. DELGRANGE ET AL: "A High-Voltage IC Driver for Large-Area AC Plasma Display Panels", DIGEST OF TECHNICAL PAPERS, SOCIETY FOR INFORMATION DISPLAY INTERNATIONAL SYMPOSIUM, 5-7 JUIN 1984, VOL.15 PAGES 103-106, XP002050571
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
EP 0880124 A1 19981125; EP 0880124 B1 20060308; DE 69833741 D1 20060504; DE 69833741 T2 20061116; FR 2763735 A1 19981127; FR 2763735 B1 19990813; JP 3365310 B2 20030108; JP H11143427 A 19990528; US 6097214 A 20000801
DOCDB simple family (application)
EP 98410053 A 19980518; DE 69833741 T 19980518; FR 9706498 A 19970522; JP 17794098 A 19980522; US 8383198 A 19980522