EP 0931292 A1 19990728 - A MICROCONTROLLER INCLUDING AN INTERNAL MEMORY UNIT AND CIRCUITRY TO GENERATE AN ASSOCIATED ENABLE SIGNAL
Title (en)
A MICROCONTROLLER INCLUDING AN INTERNAL MEMORY UNIT AND CIRCUITRY TO GENERATE AN ASSOCIATED ENABLE SIGNAL
Title (de)
MIKROCONTROLLER MIT INTERNER SPEICHEREINHEIT UND SCHALTUNG ZUR ERZEUGUNG EINES ZUGEHÖRIGEN FREIGABESIGNALS
Title (fr)
MICROCONTROLEUR COMPORTANT UNE MEMOIRE INTERNE ET UN CIRCUIT POUR GENERER UN SIGNAL DE VALIDATION ASSOCIE
Publication
Application
Priority
- US 9709545 W 19970602
- US 69663696 A 19960814
Abstract (en)
[origin: WO9807099A1] A microcontroller is presented which includes a microcontroller core, an internal memory unit, an I/O pad interface unit, and several I/O pads, all formed on a single monolithic silicon substrate. The internal memory unit is configured to store data. A chip select unit within the microcontroller core generates a dedicated internal chip select (ICS#) signal which enables storage operations within the internal memory unit. Key operating parameters of the internal memory unit are stored in a single programmable internal memory chip select register (IMCSR) located within the chip select unit. The size of the internal memory unit is fixed, eliminating the need to store size information. The internal memory chip select register contains a base address field. The base address field includes a minimum number of the highest-ordered bits of a base address of the internal memory unit required to define which non-overlapping section of the physical address space the internal memory unit is mapped into. The method of accessing the internal memory unit allows backwards compatibility with existing microcontroller products. The microcontroller core also includes an execution unit and a bus interface unit. The execution unit executes microprocessor instructions, preferably instructions from an x86 instruction set. The bus interface unit handles all data transfer operations for the microcontroller core in accordance with established protocols. The I/O pad interface unit provides the microcontroller with off-chip data transfer capability, allowing the microprocessor to read data from or write data to external devices.
IPC 1-7
IPC 8 full level
G06F 12/06 (2006.01); G06F 15/78 (2006.01)
CPC (source: EP)
G06F 15/7814 (2013.01); G06F 15/786 (2013.01)
Citation (search report)
See references of WO 9807099A1
Designated contracting state (EPC)
DE FR GB NL
DOCDB simple family (publication)
WO 9807099 A1 19980219; EP 0931292 A1 19990728; JP 2001503167 A 20010306
DOCDB simple family (application)
US 9709545 W 19970602; EP 97927936 A 19970602; JP 50969098 A 19970602