EP 0961261 A1 19991201 - Method and circuit for automatic phase and frequency adjustment of a regenerated clock in a digital image display apparatus
Title (en)
Method and circuit for automatic phase and frequency adjustment of a regenerated clock in a digital image display apparatus
Title (de)
Verfahren und Schaltung zur automatischen Phasen- und Frequenzeinstellung von einem rückgewonnenen Takt in einer digitalen Bildanzeigevorrichtung
Title (fr)
Méthode et circuit pour le réglage automatique de phase et de fréquence d'un signal d'horloge récupéré dans un appareil digital d'affichage d'image
Publication
Application
Priority
JP 14536098 A 19980527
Abstract (en)
An digital image display apparatus (IDA) converting an analog image input signal (Sia) into digital form to display images has an A/D converting unit (ADCU) for converting the analog image input signal (Sia) into a digital image signal (Sid) in a given cycle based on a clock (Scd) and phase data (Sp), an image start/termination coordinate detector (3) for detecting horizontal image start coordinates (HcS) and horizontal image termination coordinates (HcE) in a horizontal period (Ph1 - Ph2) based on the digital image signal (Sid), a horizontal synchronizing signal (Hsync) and a vertical synchronizing signal (Vsync), and a clock (Sc), an image start/termination storage (6) for storing the horizontal image start coordinates (HcS) and the horizontal image termination coordinates (HcE) related to the phase data in the A/D converting unit (ADCU), a display controller (4R) for outputting the phase data (Sp) and computing the clock count data (Scd) related to a frequency of the clock (Sc) from the horizontal image start coordinates (HcS) and the horizontal image termination coordinates (HcE). The display controller (4R) successively generates the phase data (Sp), then measures a value obtained by subtracting the horizontal image start coordinates (HcS) from the horizontal image termination coordinates (HcE) for each phase data (Sp) to successively store, and thereby automatically adjusts the number of waves of the clock (Sc) so that the minimum value among the values successively stored matches a pixel count (NHP) in an effective horizontal display period determined when the analog image input signal (Sia) is digitally generated. <IMAGE>
IPC 1-7
IPC 8 full level
CPC (source: EP)
G09G 5/008 (2013.01)
Citation (search report)
- [AD] EP 0805430 A1 19971105 - MATSUSHITA ELECTRIC IND CO LTD [JP]
- [A] EP 0791913 A2 19970827 - SEIKO EPSON CORP [JP]
- [A] PATENT ABSTRACTS OF JAPAN vol. 199, no. 511 26 December 1995 (1995-12-26)
Designated contracting state (EPC)
DE FR GB IT SE
DOCDB simple family (publication)
DOCDB simple family (application)
EP 99107443 A 19990427