Global Patent Index - EP 0974112 A1

EP 0974112 A1 2000-01-26 - METHOD FOR DESIGNING COMPLEX, DIGITAL AND INTEGRATED CIRCUITS AND A CIRCUIT STRUCTURE FOR CARRYING OUT SAID METHOD

Title (en)

METHOD FOR DESIGNING COMPLEX, DIGITAL AND INTEGRATED CIRCUITS AND A CIRCUIT STRUCTURE FOR CARRYING OUT SAID METHOD

Title (de)

VERFAHREN ZUM ENTWURF KOMPLEXER, DIGITALER UND INTEGRIERTER SCHALTUNGEN SOWIE SCHALTUNGSSTRUKTUR ZUR DURCHFÜHRUNG DES VERFAHRENS

Title (fr)

PROCEDE POUR LA CONCEPTION DE CIRCUITS NUMERIQUES ET INTEGRES COMPLEXES ET STRUCTURE DE CIRCUIT POUR LA MISE EN OEUVRE DE CE PROCEDE

Publication

EP 0974112 A1 (DE)

Application

EP 98930641 A

Priority

  • DE 9801019 W
  • DE 19714756 A
  • DE 19731043 A

Abstract (en)

[origin: WO9845794A1] The data flows of a system are allocated an arithmetic or logical function per function block (ALU-block), forming a RAM control. The ALU-blocks are specialised according to individual processing tasks of the data flows. The current status of the RAM address and RAM output data are recoupled with the ALU-blocks. During operation, the ALU-blocks alternately produce write accesses to the RAM and read accesses of all the ALU-blocks can occur with every cycle, thereby controlling the outgoing signal lines of the data flows. Registers are inserted in such a way that the ALU-blocks are placed between register levels to ensure that test patterns are generated automatically with existing CAE programs. The low use of test structures guarantees that the base circuit has good testability with a minimal test pattern rate at an early stage of the circuit design. The inventive circuit structure can also be configured as a digital signal processor.

IPC 1-7 (main, further and additional classification)

G06F 17/50; G06F 11/267

IPC 8 full level (invention and additional information)

G01R 31/28 (2006.01); G01R 31/3185 (2006.01); G06F 7/48 (2006.01); G06F 9/302 (2006.01); G06F 11/22 (2006.01); G06F 11/27 (2006.01); G06F 17/50 (2006.01)

CPC (invention and additional information)

G06F 9/3001 (2013.01); G01R 31/318591 (2013.01); G06F 7/48 (2013.01); G06F 11/27 (2013.01); G06F 17/5022 (2013.01); G06F 17/5045 (2013.01)

Citation (search report)

See references of WO 9845794A1

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU NL PT SE

EPO simple patent family

WO 9845794 A1 19981015; EP 0974112 A1 20000126; JP 2000515658 A 20001121; US 6557157 B1 20030429

INPADOC legal status


2007-04-25 [18D] DEEMED TO BE WITHDRAWN

- Ref Legal Event Code: 18D

- Effective date: 20061101

2002-01-30 [17Q] FIRST EXAMINATION REPORT

- Ref Legal Event Code: 17Q

- Effective date: 20011213

2000-01-26 [17P] REQUEST FOR EXAMINATION FILED

- Ref Legal Event Code: 17P

- Effective date: 19991020

2000-01-26 [AK] DESIGNATED CONTRACTING STATES:

- Ref Legal Event Code: AK

- Designated State(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU NL PT SE