Global Patent Index - EP 1004075 A4

EP 1004075 A4 2001-01-17 - TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR

Title (en)

TRANSLATED MEMORY PROTECTION APPARATUS FOR AN ADVANCED MICROPROCESSOR

Title (de)

SPEICHERSCHUTZEINRICHTUNG ZUM SCHUTZ GEGEN ÜBERSETZTE BEFEHLE FÜR EINEN MIKROPROZESSOR

Title (fr)

DISPOSITIF DE PROTECTION DE MEMOIRE D'INSTRUCTIONS TRADUITES POUR MICROPROCESSEUR EVOLUE

Publication

EP 1004075 A4 (EN)

Application

EP 97939380 A

Priority

US 9714117 W

Abstract (en)

[origin: WO9908191A1] A method of responding to an attempt to write a memory address including a target instruction which has been translated to a host instruction for execution by a host processor including the steps of marking a memory address including a target instruction which has been translated to a host instruction, detecting a memory address which has been marked when an attempt is made to write to the memory address, and responding to the detection of a memory address which has been marked by protecting a target instruction at the memory address until it has been assured that translations associated with the memory address will not be utilized before being updated.

IPC 1-7 (main, further and additional classification)

G06F 9/455; G06F 12/00; G06F 12/14; G06F 12/16; G06F 13/00

IPC 8 full level (invention and additional information)

G06F 9/30 (2006.01); G06F 9/318 (2006.01); G06F 9/38 (2006.01); G06F 9/455 (2006.01); G06F 12/10 (2006.01); G06F 12/14 (2006.01)

CPC (invention and additional information)

G06F 9/3812 (2013.01); G06F 9/45504 (2013.01); G06F 12/145 (2013.01)

Citation (search report)

  • [XA] KEMAL EBCIOGLU, ERIK R. ALTMAN: "DAISY: Dynamic Compilation for 100% Architecture Compatibility", INTERNET DOCUMENT: IBM RESEARCH REPORT, 8 May 1996 (1996-05-08), XP002152424, Retrieved from the Internet <URL:http://domino.watson.ibm.com/library/cyberdig.nsf/a3807c5b4823c53f85256561006324be/fd183b4dacc05b7585256593007209e7/$FILE/8502.ps.gz> [retrieved on 20001107]
  • [XA] GABRIEL M. SILBERMAN, KEMAL EBCIOLGU: "AN ARCHITECTURAL FRAMEWORK FOR MIGRATION FROM CISC TO HIGHER PERFORMANCE PLATFORMS", INTERNATIONAL CONFERENCE ON SUPERCOMPUTING, CONFERENCE PROCEEDINGS, 19 July 1992 (1992-07-19), XP000576925
  • [A] MANOJ FRANKLIN, MARK SMOTHERMAN: "A FILL-UNIT APPROACH TO MULTIPLE INSTRUCTION ISSUE", PROCEEDINGS OF THE ANNUAL INTERNATIONAL SYMPOSIUM ON MICROARCHITECTURE, November 1994 (1994-11-01), XP000874608
  • See also references of WO 9908191A1

Designated contracting state (EPC)

AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

EPO simple patent family

WO 9908191 A1 19990218; CA 2283560 A1 19990218; CA 2283560 C 20031209; EP 1004075 A1 20000531; EP 1004075 A4 20010117; JP 2001519955 A 20011023; JP 3621116 B2 20050216; KR 100421687 B1 20040310; KR 20010014096 A 20010226

INPADOC legal status


2007-02-14 [18D] DEEMED TO BE WITHDRAWN

- Effective date: 20060829

2004-03-31 [17Q] FIRST EXAMINATION REPORT

- Effective date: 20030930

2001-01-17 [A4] SUPPLEMENTARY SEARCH REPORT

- Effective date: 20001130

2001-01-17 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A4

- Designated State(s): AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

2001-01-10 [RIC1] CLASSIFICATION (CORRECTION)

- Free text: 7G 06F 9/455 A, 7G 06F 12/00 B, 7G 06F 12/14 B, 7G 06F 12/16 B, 7G 06F 13/00 B

2000-05-31 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20000313

2000-05-31 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A1

- Designated State(s): AT BE CH DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE