EP 1016212 A1 20000705 - CMOS DELAY CIRCUIT USING SUBSTRATE BIASSING
Title (en)
CMOS DELAY CIRCUIT USING SUBSTRATE BIASSING
Title (de)
CMOS VERZÖGERUNGSSCHALTUNG UNTER VERWENDUNG VON SUBSTRATVORSPANNUNG
Title (fr)
CIRCUIT CMOS A RETARD UTILISANT LA POLARISATION PAR SUBSTRAT
Publication
Application
Priority
- EP 99931253 A 19990702
- EP 9904708 W 19990702
- EP 98202357 A 19980714
Abstract (en)
[origin: WO0004638A1] A delay element (DL), for delaying a signal which propagates through the delay element (DL) by a delay, comprises a field effect transistor (T>1<) having a source, a drain, a gate, and a back-gate (BG). The back-gate (BG) is arranged to receive a control voltage (V>cntrl<). The control voltage (V>cntrl<) controls a current through the field effect transistor (T>1<). As a consequence, the delay is also controlled by the control voltage (V>cntrl<).
IPC 1-7
IPC 8 full level
H03K 3/354 (2006.01); H03K 5/13 (2006.01); H03L 7/099 (2006.01)
CPC (source: EP KR)
H03K 5/133 (2013.01 - EP); H03K 5/134 (2014.07 - KR)
Citation (search report)
See references of WO 0004638A1
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE
DOCDB simple family (publication)
WO 0004638 A1 20000127; EP 1016212 A1 20000705; JP 2002520979 A 20020709; KR 20010030591 A 20010416
DOCDB simple family (application)
EP 9904708 W 19990702; EP 99931253 A 19990702; JP 2000560661 A 19990702; KR 20007002633 A 20000313