Global Patent Index - EP 1016212 A1

EP 1016212 A1 2000-07-05 - CMOS DELAY CIRCUIT USING SUBSTRATE BIASSING

Title (en)

CMOS DELAY CIRCUIT USING SUBSTRATE BIASSING

Title (de)

CMOS VERZÖGERUNGSSCHALTUNG UNTER VERWENDUNG VON SUBSTRATVORSPANNUNG

Title (fr)

CIRCUIT CMOS A RETARD UTILISANT LA POLARISATION PAR SUBSTRAT

Publication

EP 1016212 A1 (EN)

Application

EP 99931253 A

Priority

  • EP 99931253 A
  • EP 9904708 W
  • EP 98202357 A

Abstract (en)

[origin: WO0004638A1] A delay element (DL), for delaying a signal which propagates through the delay element (DL) by a delay, comprises a field effect transistor (T>1<) having a source, a drain, a gate, and a back-gate (BG). The back-gate (BG) is arranged to receive a control voltage (V>cntrl<). The control voltage (V>cntrl<) controls a current through the field effect transistor (T>1<). As a consequence, the delay is also controlled by the control voltage (V>cntrl<).

IPC 1-7 (main, further and additional classification)

H03K 5/13

IPC 8 full level (invention and additional information)

H03K 3/354 (2006.01); H03K 5/13 (2006.01); H03L 7/099 (2006.01)

CPC (invention and additional information)

H03K 5/133 (2013.01)

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE

EPO simple patent family

WO 0004638 A1 20000127; EP 1016212 A1 20000705; JP 2002520979 A 20020709

INPADOC legal status


2003-12-03 [18D] DEEMED TO BE WITHDRAWN

- Effective date: 20030603

2003-03-05 [17Q] FIRST EXAMINATION REPORT

- Effective date: 20030121

2000-09-20 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20000727

2000-07-05 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A1

- Designated State(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE