Global Patent Index - EP 1081572 A1

EP 1081572 A1 2001-03-07 - Supply circuit with voltage selector

Title (en)

Supply circuit with voltage selector

Title (de)

Versorgungsschaltung mit Spannungswähler

Title (fr)

Circuit d'alimentation à sélecteur de tension

Publication

EP 1081572 A1 (FR)

Application

EP 00410109 A

Priority

FR 9911033 A

Abstract (en)

The circuit receives several supply voltages (V1,V2,V3) via connections (L1,L2,L3) each of which is connected to respective switches (T1,T2,T3). At least one of the switches (T1) is a first MOS transistor of P conductivity type connected between the line (L1) and a common output terminal (S). The circuit also includes: - a second transistor (T3) of P conductivity type, connected between the grid of the first transistor (T1) and a node (N) maintained at the highest of the supply voltages; - a third transistor (T4), of N conductivity type, of less conductivity in the conducting state as the first transistor (T1), connected between the grid of the first transistor (T1) and a reference potential, and; - a fourth transistor (T5), of P type of conductivity, whose source is connected to a supply line associated with a switch, and whose drain is connected to a current source (R1) and to the grids of the second (T3), third (T4) and fourth (T5) transistors..

Abstract (fr)

L'invention concerne un circuit d'alimentation recevant plusieurs tensions d'alimentation (V1, V2, V3) sur des commutateurs respectifs (T1, T2, T3), au moins un des commutateurs (T1) étant un premier transistor PMOS connecté entre une des tensions d'alimentation (L1) et une borne de sortie commune (S), ce commutateur étant associé à un deuxième transistor (T3) PMOS relié entre la grille du premier transistor et un noeud d'alimentation (N) maintenu à la plus haute des autres tensions d'alimentation, à un troisième transistor (T4) NMOS moins conducteur à l'état passant que le deuxième transistor, relié entre la grille du premier transistor et la masse, et à un quatrième transistor (T5) PMOS dont la source est reliée à la ligne d'alimentation du commutateur et dont le drain est relié à la masse par l'intermédiaire d'une source de courant (R1) et aux grilles des deuxième, troisième et quatrième transistors. <IMAGE>

IPC 1-7 (main, further and additional classification)

G05F 1/59

IPC 8 full level (invention and additional information)

G05F 1/59 (2006.01)

CPC (invention and additional information)

G05F 1/59 (2013.01); Y10T 307/696 (2015.04); Y10T 307/832 (2015.04)

Citation (search report)

Designated contracting state (EPC)

DE FR GB IT

EPO simple patent family

EP 1081572 A1 20010307; EP 1081572 B1 20041103; DE 60015464 D1 20041209; FR 2798014 A1 20010302; FR 2798014 B1 20020329; US 6566935 B1 20030520

INPADOC legal status


2008-11-28 [PG25 GB] LAPSED IN A CONTRACTING STATE ANNOUNCED VIA POSTGRANT INFORM. FROM NAT. OFFICE TO EPO

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- Effective date: 20070830

2008-10-31 [PG25 FR] LAPSED IN A CONTRACTING STATE ANNOUNCED VIA POSTGRANT INFORM. FROM NAT. OFFICE TO EPO

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2008-07-25 [REG FR ST] NOTIFICATION OF LAPSE

- Effective date: 20080430

2008-04-23 [GBPC] GB: EUROPEAN PATENT CEASED THROUGH NON-PAYMENT OF RENEWAL FEE

- Effective date: 20070830

2006-08-30 [PGFP GB] POSTGRANT: ANNUAL FEES PAID TO NATIONAL OFFICE

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- Year of fee payment: 7

2006-08-08 [PGFP FR] POSTGRANT: ANNUAL FEES PAID TO NATIONAL OFFICE

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2005-10-26 [26N] NO OPPOSITION FILED

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2005-02-04 [PG25 DE] LAPSED IN A CONTRACTING STATE ANNOUNCED VIA POSTGRANT INFORM. FROM NAT. OFFICE TO EPO

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- Free text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

- Effective date: 20050204

2004-12-09 [REF] CORRESPONDS TO:

- Document: DE 60015464 P 20041209

2004-11-24 [GBT] GB: TRANSLATION OF EP PATENT FILED (GB SECTION 77(6)(A)/1977)

2004-11-03 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: B1

- Designated State(s): DE FR GB IT

2004-11-03 [REG GB FG4D] EUROPEAN PATENT GRANTED

- Free text: NOT ENGLISH

2004-11-03 [PG25 IT] LAPSED IN A CONTRACTING STATE ANNOUNCED VIA POSTGRANT INFORM. FROM NAT. OFFICE TO EPO

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- Free text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

- Effective date: 20041103

2004-03-03 [17Q] FIRST EXAMINATION REPORT

- Effective date: 20040116

2001-12-19 [RAP1] TRANSFER OF RIGHTS OF AN EP PUBLISHED APPLICATION

- Owner name: STMICROELECTRONICS S.A.

2001-11-28 [AKX] PAYMENT OF DESIGNATION FEES

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2001-10-31 [17P] REQUEST FOR EXAMINATION FILED

- Effective date: 20010831

2001-03-14 [RIN1] INVENTOR (CORRECTION)

- Inventor name: RENOUS, CLAUDE

2001-03-07 [AK] DESIGNATED CONTRACTING STATES:

- Kind Code of Ref Document: A1

- Designated State(s): DE FR GB IT

2001-03-07 [AX] REQUEST FOR EXTENSION OF THE EUROPEAN PATENT TO

- Free text: AL;LT;LV;MK;RO;SI