EP 1135802 A1 20010926 - THREE-DIMENSIONAL PACKAGING TECHNOLOGY FOR MULTI-LAYERED INTEGRATED CIRCUITS
Title (en)
THREE-DIMENSIONAL PACKAGING TECHNOLOGY FOR MULTI-LAYERED INTEGRATED CIRCUITS
Title (de)
DREIDIMENSIONALE VERPACKUNGSTECHNOLOGIE FÜR MEHRSCHICHTIGE INTEGRIERTE SCHALTUNGEN
Title (fr)
ASSEMBLAGE TRIDIMENSIONNEL POUR CIRCUITS INTEGRES MULTICOUCHES
Publication
Application
Priority
US 9815477 W 19980727
Abstract (en)
[origin: WO0007240A1] Disclosed is method and apparatus (1) for packaging multilayered integrated circuit (IC) chips (2), on which logic circuits and/or memory arrays are disposed and interconnected in a novel way permitting the addressing (i.e. selection) of the logic circuits and/or arrays on these IC chip layers using a minimum number of connections and with the shortest propagation delays.
IPC 1-7
IPC 8 full level
G11C 5/00 (2006.01); G11C 5/06 (2006.01); H01L 21/98 (2006.01); H01L 23/467 (2006.01); H01L 25/065 (2006.01); H01L 25/07 (2006.01); H01L 25/18 (2006.01); G02B 6/43 (2006.01)
CPC (source: EP KR)
G11C 5/02 (2013.01 - EP); G11C 5/04 (2013.01 - EP); G11C 5/063 (2013.01 - EP); H01L 23/467 (2013.01 - EP); H01L 23/50 (2013.01 - KR); H01L 25/0657 (2013.01 - EP); H01L 25/18 (2013.01 - EP); H01L 25/50 (2013.01 - EP); G02B 6/43 (2013.01 - EP); H01L 2225/06551 (2013.01 - EP); H01L 2225/06589 (2013.01 - EP); H01L 2924/0002 (2013.01 - EP)
Designated contracting state (EPC)
DE FR GB IT
DOCDB simple family (publication)
WO 0007240 A1 20000210; AU 8592098 A 20000221; CA 2338335 A1 20000210; EP 1135802 A1 20010926; EP 1135802 A4 20040825; JP 2002521844 A 20020716; KR 20010106420 A 20011129
DOCDB simple family (application)
US 9815477 W 19980727; AU 8592098 A 19980727; CA 2338335 A 19980727; EP 98937138 A 19980727; JP 2000562952 A 19980727; KR 20017001145 A 20010127