EP 1269418 A1 20030102 - TILED GRAPHICS ARCHITECTURE
Title (en)
TILED GRAPHICS ARCHITECTURE
Title (de)
FLIESENARTIGABBILDUNGSARCHITEKTUR
Title (fr)
ARCHITECTURE GRAPHIQUE EN MOSAIQUES
Publication
Application
Priority
- US 0107225 W 20010306
- US 54061600 A 20000331
Abstract (en)
[origin: WO0175804A1] A method and apparatus for reducing memory bandwidth utilization in a tiled graphics architecture is disclosed. In one embodiment, a microprocessor reads vertex data for a graphics primitive from graphics memory. The processor determines with which bins the graphics primitive intersects. Assuming that the processor determines that the graphics primitive intersects a first and a second bin, the processor writes the vertex data for the graphics primitve to a first bin storage area in graphics memory. The processor then writes a pointer to a second bin storage area. The pointer indicates the location in memory of the actual vertex data.
IPC 1-7
IPC 8 full level
G06T 15/00 (2011.01)
CPC (source: EP KR)
G06T 1/60 (2013.01 - KR); G06T 15/005 (2013.01 - EP)
Citation (search report)
See references of WO 0175804A1
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
DOCDB simple family (publication)
WO 0175804 A1 20011011; AU 5695501 A 20011015; CN 102842145 A 20121226; CN 102842145 B 20160824; CN 1430769 A 20030716; CN 1430769 B 20120530; EP 1269418 A1 20030102; HK 1049537 A1 20030516; JP 2003529860 A 20031007; KR 100550240 B1 20060208; KR 20030005253 A 20030117; TW I233573 B 20050601
DOCDB simple family (application)
US 0107225 W 20010306; AU 5695501 A 20010306; CN 01809891 A 20010306; CN 201210080502 A 20010306; EP 01930417 A 20010306; HK 03101674 A 20030307; JP 2001573406 A 20010306; KR 20027013055 A 20010306; TW 90107594 A 20010417