EP 1305827 A1 20030502 - SEMICONDUCTOR MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME
Title (en)
SEMICONDUCTOR MEMORY CELL ARRANGEMENT AND METHOD FOR PRODUCING THE SAME
Title (de)
HALBLEITERSPEICHER-ZELLENANORDNUNG UND VERFAHREN ZU DEREN HERSTELLUNG
Title (fr)
AGENCEMENT DE CELLULES DE MEMOIRE A SEMICONDUCTEURS ET SON PROCEDE DE REALISATION
Publication
Application
Priority
- DE 0102798 W 20010723
- DE 10038728 A 20000731
Abstract (en)
[origin: US2003169629A1] A semiconductor memory cell configuration includes dynamic memory cells respectively having a trench capacitor and a vertical selection transistor, the memory cells being disposed in matrix form, the trench capacitors and the associated vertical selection transistors following one another in each case in the form of rows and/or columns.
IPC 1-7
IPC 8 full level
H01L 21/8242 (2006.01); H01L 27/108 (2006.01)
CPC (source: EP KR US)
H10B 12/00 (2023.02 - KR); H10B 12/0383 (2023.02 - EP US)
Citation (search report)
See references of WO 0211200A1
Designated contracting state (EPC)
AT BE CH CY DE FR GB IE IT LI
DOCDB simple family (publication)
US 2003169629 A1 20030911; US 6853023 B2 20050208; DE 10038728 A1 20020221; EP 1305827 A1 20030502; JP 2004505466 A 20040219; JP 4004949 B2 20071107; KR 100506336 B1 20050805; KR 20030019639 A 20030306; TW 513801 B 20021211; WO 0211200 A1 20020207; WO 0211200 A8 20020411
DOCDB simple family (application)
US 35678003 A 20030131; DE 0102798 W 20010723; DE 10038728 A 20000731; EP 01956376 A 20010723; JP 2002516826 A 20010723; KR 20037001413 A 20030130; TW 90118615 A 20010731