Global Patent Index - EP 1390941 A1

EP 1390941 A1 20040225 - ACTIVE MATRIX ADDRESSED BISTABLE REFLECTIVE CHOLESTERIC DISPLAYS AND GRAPHIC CONTROLLERS AND OPERATING METHODS THEREFOR

Title (en)

ACTIVE MATRIX ADDRESSED BISTABLE REFLECTIVE CHOLESTERIC DISPLAYS AND GRAPHIC CONTROLLERS AND OPERATING METHODS THEREFOR

Title (de)

BISTABILE REFLEKTIVE CHOLESTERISCHE ANZEIGEN MIT AKTIVMATRIXADRESSIERUNG UND GRAPHISCHE STEUERUNGEN UND BETRIEBSVERFAHREN DAFÜR

Title (fr)

CONTROLEURS GRAPHIQUES ET AFFICHEURS A CRISTAUX CHOLESTERIQUES REFLECHISSANTS BISTABLES ADRESSES PAR MATRICE ACTIVE ET MODALITES DE MISE EN OEUVRE

Publication

EP 1390941 A1 20040225 (EN)

Application

EP 01968048 A 20010912

Priority

  • US 0126017 W 20010912
  • US 83631901 A 20010418
  • US 83632901 A 20010418
  • US 83664001 A 20010418

Abstract (en)

[origin: WO02086855A1] A low power color display system (1) includes a memory (502), which stores color data and status bits corresponding to a plurality of pixels, status logic (504), which generates the status bits responsive to receipt of color data for a respective one of the pixels, a data generator (520, 522), which generates voltage data corresponding to the pixels based on the color data and the status bits for each of the pixels, driver circuitry (200), which generates voltage signals responsive to receipt of the voltage data for each of the pixels, and a bistable liquid crystal display (LCD) (100) having multiple cells arranged in a matrix, each cell corresponding to a pixel, the LCD being responsive to the voltage signals. Preferably, the system also includes a power supply (400) which provides power to the driver circuitry (200), and a power manager (518), the latter turning the power supply ON when the data generator is in the first operating mode and turning the power supply OFF when the data generator is in the second operating mode. The data generator (520, 522) generates the voltage data for a corresponding pixel N times to thereby permit application of the voltage signal corresponding to the pixel data to the LCD N time, where N is an integer established by the status bits.

IPC 1-7

G09G 3/36; G09G 5/00

IPC 8 full level

G09G 3/36 (2006.01); G09G 5/36 (2006.01)

CPC (source: EP)

G09G 3/3651 (2013.01); G09G 5/363 (2013.01); G09G 2300/0486 (2013.01); G09G 2310/04 (2013.01); G09G 2320/041 (2013.01); G09G 2320/103 (2013.01); G09G 2330/022 (2013.01)

Citation (search report)

See references of WO 02086855A1

Designated contracting state (EPC)

AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR

DOCDB simple family (publication)

WO 02086855 A1 20021031; EP 1390941 A1 20040225

DOCDB simple family (application)

US 0126017 W 20010912; EP 01968048 A 20010912