EP 1415233 A1 20040506 - EFFICIENT INTERRUPT SYSTEM FOR SYSTEM ON CHIP DESIGN
Title (en)
EFFICIENT INTERRUPT SYSTEM FOR SYSTEM ON CHIP DESIGN
Title (de)
EFFIZIENTES UNTERBRECHUNGSSYSTEM FÜR ON-CHIP SYSTEMENENTWURF
Title (fr)
SYSTEME D'INTERRUPTION EFFICACE POUR SYSTEME SUR PUCE
Publication
Application
Priority
- IB 0202801 W 20020702
- US 91860301 A 20010730
Abstract (en)
[origin: WO03012658A1] A method (400) and system (10) for managing interrupts in a system on a chip design that includes multiple processors (100a, 100b, ..., 100n) coupled to multiple peripheral devices (120a, 120b, ..., 120m). A plurality of interconnected interrupt controllers (110a, 110b, ..., 110n) are coupled between the processors and the peripheral devices. Interrupts generated by the peripheral devices are received by all of the interrupt controllers. In one embodiment, an interrupt controller is paired with a processor. Each interrupt controller can identify which interrupts will be passed to its respective processor. The interrupt controllers work in concert to pass each interrupt to a particular processor.
IPC 1-7
IPC 8 full level
G06F 15/16 (2006.01); G06F 9/46 (2006.01); G06F 13/24 (2006.01); G06F 13/26 (2006.01)
CPC (source: EP)
G06F 13/26 (2013.01)
Citation (search report)
See references of WO 03012658A1
Designated contracting state (EPC)
AT BE CH CY DE DK ES FI FR GB GR IE IT LI LU MC NL PT SE TR
DOCDB simple family (publication)
WO 03012658 A1 20030213; CN 1535427 A 20041006; EP 1415233 A1 20040506; JP 2004537809 A 20041216
DOCDB simple family (application)
IB 0202801 W 20020702; CN 02814889 A 20020702; EP 02745724 A 20020702; JP 2003517765 A 20020702