EP 1665529 A2 20060607 - MASTER LATCH CIRCUIT WITH SIGNAL LEVEL DISPLACEMENT FOR A DYNAMIC FLIP-FLOP
Title (en)
MASTER LATCH CIRCUIT WITH SIGNAL LEVEL DISPLACEMENT FOR A DYNAMIC FLIP-FLOP
Title (de)
MASTER-LATCHSCHALTUNG MIT SIGNALPEGELVERSCHIEBUNG FÜR EIN DYNAMISCHES FLIP-FLOP
Title (fr)
CIRCUIT DE VERROUILLAGE MAITRE A DECALAGE DE NIVEAU DE SIGNAL POUR UNE BASCULE DYNAMIQUE
Publication
Application
Priority
- EP 2004009853 W 20040903
- DE 10343565 A 20030919
Abstract (en)
[origin: DE10343565B3] The master latch circuit (10) has a signal delay circuit (13) for delaying a received clock signal (Clk) and a circuit node (14) which is charged to an operating voltage during a charging phase and discharged in dependence on an applied data signal (D) in an evaluation phase, the circuit node coupled to a reference potential via at least one capacitor (15).
IPC 1-7
IPC 8 full level
H03K 3/037 (2006.01); H03K 3/356 (2006.01)
CPC (source: EP US)
H03K 3/037 (2013.01 - EP US); H03K 3/356121 (2013.01 - EP US)
Designated contracting state (EPC)
DE FR GB
DOCDB simple family (publication)
DE 10343565 B3 20050310; CN 100433552 C 20081112; CN 1816967 A 20060809; EP 1665529 A2 20060607; JP 2006515494 A 20060525; JP 4575300 B2 20101104; US 2006273838 A1 20061207; WO 2005039050 A2 20050428; WO 2005039050 A3 20050609
DOCDB simple family (application)
DE 10343565 A 20030919; CN 200480018787 A 20040903; EP 04764805 A 20040903; EP 2004009853 W 20040903; JP 2005518691 A 20040903; US 56304004 A 20040903