EP 1728139 A2 20061206 - PROGRAMMABLE CLOCK GENERATION
Title (en)
PROGRAMMABLE CLOCK GENERATION
Title (de)
PROGRAMMIERBARE TAKTERZEUGUNG
Title (fr)
GENERATION D'HORLOGE PROGRAMMABLE
Publication
Application
Priority
- IB 2005050713 W 20050228
- EP 04100876 A 20040304
- EP 05708859 A 20050228
Abstract (en)
[origin: WO2005088421A2] A mechanism for generating a clock signal for an integrated circuit, or part of one, so that the frequency thereof can be safely changed continuously (i.e. with a gradual frequency change) without spurious signals or glitches being created on the clock output line. A electronic device according to an exemplary embodiment, comprises a multiplexer (10) having two input signals, the second of which is a delayed version of the first, created by feeding the input to the multiplexer (10) via a set of generic combinatorial delay elements (12) and the multiplexer output id fed to the output (Out) via an inverter (14). The element further comprises a D-type flip-flop (16) having as its "D" input a programming signal (Fk), and the two outputs "Q" and "Qn" from the D-type flip-flop provided respective drive signals to the multiplexer (10). The delay of the output signal (Out) with respect to the input signal (In) depends on the value of the programming signal (Fk), which is synchronized on the rising edge of the local clock (sync_ck).
IPC 8 full level
CPC (source: EP)
Citation (search report)
See references of WO 2005088421A2
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2005088421 A2 20050922; WO 2005088421 A3 20060316; CN 100422901 C 20081001; CN 1926494 A 20070307; EP 1728139 A2 20061206; JP 2007526575 A 20070913
DOCDB simple family (application)
IB 2005050713 W 20050228; CN 200580006636 A 20050228; EP 05708859 A 20050228; JP 2007501424 A 20050228