EP 1779256 A2 20070502 - PROGRAMMABLE PROCESSOR ARCHITECTURE
Title (en)
PROGRAMMABLE PROCESSOR ARCHITECTURE
Title (de)
PROGRAMMIERBARE PROZESSORARCHITEKTUR
Title (fr)
ARCHITECTURE DE PROCESSEUR PROGRAMMABLE
Publication
Application
Priority
- US 2005024867 W 20050712
- US 58769104 P 20040713
- US 59841704 P 20040802
Abstract (en)
[origin: WO2006017339A2] One embodiment of the present includes a heterogenous, high-performance, scalable processor having at least one W-type sub-processor capable of processing W bits in parallel, W being an integer value, at least one N-type sub-processor capable of processing N bits in parallel, N being an integer value wherein and smaller than W by a factor of two. The processor further includes a shared bus coupling the at least one W-type sub-processor and at least one N-type subprocessor and memory shared coupled to the at least one W-type sub-processor and the at least one N-type sub-processor, wherein the W-type sub-processor rearranges memory to accommodate execution of applications allowing for fast operations.
IPC 8 full level
G06F 15/76 (2006.01)
CPC (source: EP KR)
G06F 9/3001 (2013.01 - EP); G06F 9/30018 (2013.01 - EP); G06F 9/30032 (2013.01 - EP); G06F 9/3885 (2013.01 - EP); G06F 15/00 (2013.01 - KR); G06F 15/76 (2013.01 - KR); G06F 15/7864 (2013.01 - EP)
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HU IE IS IT LI LT LU LV MC NL PL PT RO SE SI SK TR
DOCDB simple family (publication)
WO 2006017339 A2 20060216; WO 2006017339 A3 20060406; CA 2572954 A1 20060216; EP 1779256 A2 20070502; EP 1779256 A4 20071128; JP 2008507039 A 20080306; KR 20070055487 A 20070530
DOCDB simple family (application)
US 2005024867 W 20050712; CA 2572954 A 20050712; EP 05771043 A 20050712; JP 2007521614 A 20050712; KR 20077000909 A 20070112