EP 1784701 A1 20070516 - CURRENT MIRROR ARRANGEMENT
Title (en)
CURRENT MIRROR ARRANGEMENT
Title (de)
STROMSPIEGELANORDNUNG
Title (fr)
SYSTEME DE MIROIR DE COURANT
Publication
Application
Priority
- EP 2005009398 W 20050831
- DE 102004042354 A 20040901
Abstract (en)
[origin: WO2006024525A1] The invention relates to a current mirror arrangement wherein two current mirror transistors (2, 3) form a current mirror. Two cascade transistors (11, 12) are interconnected with the two current mirror transistors (2, 3), forming a cascade stage. Said cascade transistors (11, 12) respectively comprise a plurality of partial transistors (13, 14, 15; 16, 17, 18) that are interconnected in series in terms of the controlled sections thereof. In this way, the connection nodes of the current mirror transistors can be connected to a connection node between two partial transistors (14, 15). This, in turn, causes an enlargement of the input voltage range for a current source (4) that supplies an input current for the current mirror.
IPC 8 full level
G05F 3/26 (2006.01)
CPC (source: EP US)
G05F 3/262 (2013.01 - EP US)
Citation (search report)
See references of WO 2006024525A1
Citation (examination)
- US 5952884 A 19990914 - IDE SATOSHI [JP]
- NOREN K.V. ET AL: "The Circuits and Filters Handbook, Second Edition. Chapter 56: Analog Circuit Cells", 31 December 2003, WAI-KAI CHEN (EDITOR), CRC PRESS, BOCA RATON, US
- YAN S.; SANCHEZ-SINENCIO E.: "Low voltage Analog Circuit Design Techniques: A Tutorial", IEICE TRANS. ANALOG INTEGRATED CIRCUITS AND SYSTEMS, vol. E00-A, no. 2, 2 February 2000 (2000-02-02), pages 1 - 17
Designated contracting state (EPC)
GB IT
DOCDB simple family (publication)
DE 102004042354 A1 20060309; DE 102004042354 B4 20080619; EP 1784701 A1 20070516; US 2007290740 A1 20071220; WO 2006024525 A1 20060309
DOCDB simple family (application)
DE 102004042354 A 20040901; EP 05790411 A 20050831; EP 2005009398 W 20050831; US 57420705 A 20050831