EP 2124125 A1 20091125 - Process and temperature compensation in CMOS circuits
Title (en)
Process and temperature compensation in CMOS circuits
Title (de)
Verfahren und Temperaturausgleich in CMOS-Schaltungen
Title (fr)
Processus et compensation de température dans des circuits CMOS
Publication
Application
Priority
EP 08156699 A 20080521
Abstract (en)
A circuit arrangement using CMOS technology is described comprising at least a first circuit (10,20) and a second, compensation circuit (50) for adaptively generating a biasing parameter (Vbias) for counter-acting temperature and process variations in the first circuit (10,20). The second circuit (50) is based on a constant-g m bias generator and comprises a NMOS transistor (NM R ) operating in ohmic region. The second circuit (50) comprises two stages (51,52) with a substantially identical structure.
IPC 8 full level
G05F 3/26 (2006.01)
CPC (source: EP)
G05F 3/26 (2013.01)
Citation (search report)
- [X] US 6407623 B1 20020618 - BAZARJANI SEYFOLLAH [US], et al
- [A] US 5532650 A 19960702 - IGARASHI SADAO [JP]
- [A] EP 0748044 A2 19961211 - ANALOG DEVICES INC [US]
- [A] US 6535068 B1 20030318 - LYNAUGH KEVIN JOHN [US]
- [A] US 2007075699 A1 20070405 - CHIH YUE-DER [TW]
- [A] HENRI J OGUEY ET AL: "CMOS Current Reference Without Resistance", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 32, no. 7, 1 July 1997 (1997-07-01), XP011060518, ISSN: 0018-9200
- [A] DAI Y ET AL: "Threshold voltage based CMOS voltage reference", IEE PROCEEDINGS: CIRCUITS DEVICES AND SYSTEMS, INSTITUTION OF ELECTRICAL ENGINEERS, STENVENAGE, GB, vol. 151, no. 1, 26 January 2004 (2004-01-26), pages 58 - 62, XP006021288, ISSN: 1350-2409
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR
Designated extension state (EPC)
AL BA MK RS
DOCDB simple family (publication)
DOCDB simple family (application)
EP 08156699 A 20080521