EP 2335374 A1 20110622 - DATA SAMPLING CIRCUIT AND METHOD FOR CLOCK AND DATA RECOVERY
Title (en)
DATA SAMPLING CIRCUIT AND METHOD FOR CLOCK AND DATA RECOVERY
Title (de)
DATENABTASTSCHALTUNG UND VERFAHREN ZUR TAKT- UND DATENWIEDERGEWINNUNG
Title (fr)
CIRCUIT D'ÉCHANTILLONNAGE DE DONNÉES ET PROCÉDÉ DE RÉCUPÉRATION D'HORLOGE ET DE DONNÉES
Publication
Application
Priority
US 2008011416 W 20081002
Abstract (en)
[origin: WO2010039108A1] A clock and data recovery circuit and method are used in a digital data communications system. The circuit and method are effectively employed for high speed, burst-mode transmission and allow rapid recovery of the clock and data signals without the need for an extended header, and notwithstanding the presence of substantial timing jitter. The method adaptively selects from among three delay times for the extraction of data by identifying a frequently recurring incoming pattern in the incoming data. The delay time is selected in a manner that insures that the same pattern is present in the reconstructed, resynchronized output data.
IPC 8 full level
H04L 7/00 (2006.01)
CPC (source: EP)
H03L 7/06 (2013.01); H03L 7/0805 (2013.01); H04L 7/0338 (2013.01)
Designated contracting state (EPC)
AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR
Designated extension state (EPC)
AL BA MK RS
DOCDB simple family (publication)
WO 2010039108 A1 20100408; CA 2774482 A1 20100408; CA 2774482 C 20151201; EP 2335374 A1 20110622; EP 2335374 A4 20120328
DOCDB simple family (application)
US 2008011416 W 20081002; CA 2774482 A 20081002; EP 08877195 A 20081002