Global Patent Index - EP 2718780 A1

EP 2718780 A1 20140416 - APPARATUS FOR GLITCHLESS CLOCK DIVIDER WITH FAST CLOCK CHANGE AND METHOD THEREOF

Title (en)

APPARATUS FOR GLITCHLESS CLOCK DIVIDER WITH FAST CLOCK CHANGE AND METHOD THEREOF

Title (de)

VORRICHTUNG FÜR STÖRUNGSFREIEN TAKTTEILER MIT SCHNELLER TAKTVERÄNDERUNG UND VERFAHREN DAFÜR

Title (fr)

APPAREIL POUR DIVISEUR D'HORLOGE SANS DÉFORMATION AVEC CHANGEMENT D'HORLOGE RAPIDE, ET PROCÉDÉ ASSOCIÉ

Publication

EP 2718780 A1 20140416 (EN)

Application

EP 11867485 A 20110609

Priority

FI 2011050538 W 20110609

Abstract (en)

[origin: WO2012168533A1] An apparatus comprising a clock shaper (510) configured to derive a frequency of a reference clock signal (501) into a plurality of n frequencies associated to a plurality of n gated clocks, Clock 0, Clock 1,..., Clock n-1 (571-0, 571-1,..., 571-n-1), and configured to generate a plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m), where n is a number of the gated clocks and m corresponds to a divisor; a plurality of n coupled clock selection and gating units (550-0, 550-1,..., 550-n-1) receiving the reference clock (501) and the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m), and configured to select one of the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m) and to gate to an output clock (571-0, 571-1,..., 571-n-1); and a phase decoding unit (530) configured to decode the plurality of m clock enable signals (511-1, 511-2, 511-3, 511-4,..., 511-m) based on a plurality of received division value per clock signals, and configured to generate a plurality of n clock selection signals (531-0, 531-1,..., 531-n-1), wherein one of the plurality of n clock selection signals (531-0, 531-1 531 -n-1) corresponds to a selected frequency of one of the plurality of frequencies of the plurality of n gated clocks (571-1, 571-2,..., 571-n-1); wherein the plurality of n coupled clock selection and gating units (550-0, 550-1 550-n-1) are responsive to the plurality of n clock selection signals (531-0, 531-1 531 -n-1) to generate the output clock (571-0, 571-1,..., 571 -n-1) with the selected frequency.

IPC 8 full level

G06F 1/08 (2006.01); G06F 1/06 (2006.01); H03K 23/66 (2006.01)

CPC (source: EP)

G06F 1/06 (2013.01); G06F 1/08 (2013.01); H03K 23/667 (2013.01)

Designated contracting state (EPC)

AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DOCDB simple family (publication)

WO 2012168533 A1 20121213; EP 2718780 A1 20140416; EP 2718780 A4 20150225

DOCDB simple family (application)

FI 2011050538 W 20110609; EP 11867485 A 20110609