EP 2831918 A4 20151118 - METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW
Title (en)
METHOD OF ONO INTEGRATION INTO LOGIC CMOS FLOW
Title (de)
VERFAHREN ZUR ONO-INTEGRATION IN EINE LOGISCHE CMOS-STRÖMUNG
Title (fr)
PROCÉDÉ D'INTÉGRATION ONO DANS UN FLUX CMOS LOGIQUE
Publication
Application
Priority
- US 201213434347 A 20120329
- US 2013030874 W 20130313
Abstract (en)
[origin: WO2013148196A1] An embodiment of a method of integration of a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming a pad dielectric layer of a MOS device above a first region of a substrate; forming a channel of the memory device from a thin film of semiconducting material overlying a surface above a second region of the substrate, the channel connecting a source and drain of the memory device; forming a patterned dielectric stack overlying the channel above the second region, the patterned dielectric stack comprising a tunnel layer, a charge-trapping layer, and a sacrificial top layer; simultaneously removing the sacrificial top layer from the second region of the substrate, and the pad dielectric layer from the first region of the substrate; and simultaneously forming a gate dielectric layer above the first region of the substrate and a blocking dielectric layer above the charge-trapping layer.
IPC 8 full level
H01L 29/792 (2006.01); H10B 41/42 (2023.01); H01L 21/28 (2006.01); H01L 29/51 (2006.01); H01L 29/66 (2006.01); H10B 41/44 (2023.01); H10B 41/49 (2023.01); H10B 43/27 (2023.01); H10B 43/30 (2023.01); H10B 43/35 (2023.01); H10B 43/40 (2023.01); H10B 69/00 (2023.01)
CPC (source: CN EP KR)
H01L 29/40117 (2019.08 - EP); H01L 29/42328 (2013.01 - EP); H01L 29/513 (2013.01 - CN EP KR); H01L 29/518 (2013.01 - CN EP KR); H01L 29/66833 (2013.01 - CN EP KR); H01L 29/792 (2013.01 - CN); H01L 29/7926 (2013.01 - CN EP KR); H10B 43/35 (2023.02 - CN KR); H10B 43/40 (2023.02 - EP)
Citation (search report)
- [Y] US 8071453 B1 20111206 - RAMKUMAR KRISHNASWAMY [US], et al
- [Y] US 2005173766 A1 20050811 - CHAE HEE-SOON [KR], et al
- [Y] US 2006115978 A1 20060601 - SPECHT MICHAEL [DE], et al
- [A] US 8063434 B1 20111122 - POLISHCHUK IGOR [US], et al
- [YA] JOO HYUNG YOU ET AL: "Effect of the trap density and distribution of the silicon nitride layer on the retention characteristics of charge trap flash memory devices", SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES (SISPAD), 2011 INTERNATIONAL CONFERENCE ON, IEEE, 8 September 2011 (2011-09-08), pages 199 - 202, XP031972658, ISBN: 978-1-61284-419-0, DOI: 10.1109/SISPAD.2011.6035085
- [YA] PEIQI XUAN ET AL: "FinFET SONOS Flash Memory for Embedded Applications", INTERNATIONAL ELECTRON DEVICES MEETING 2003. IEDM. TECHNICAL DIGEST. WASHINGTON, DC, DEC 8 - 10, 2003; [INTERNATIONAL ELECTRON DEVICES MEETING], NEW YORK, NY : IEEE, US, 8 December 2003 (2003-12-08), pages 609 - 612, XP010684085, ISBN: 978-0-7803-7872-8
- See also references of WO 2013148196A1
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
DOCDB simple family (publication)
WO 2013148196 A1 20131003; CN 104321877 A 20150128; CN 104321877 B 20180914; CN 108899273 A 20181127; CN 108899273 B 20240209; EP 2831918 A1 20150204; EP 2831918 A4 20151118; EP 3166147 A2 20170510; EP 3166147 A3 20170816; EP 3866199 A1 20210818; JP 2015512567 A 20150427; JP 6328607 B2 20180523; KR 102079835 B1 20200220; KR 20150105186 A 20150916; KR 20190082327 A 20190709; TW 201347150 A 20131116; TW 201743437 A 20171216; TW I599020 B 20170911; TW I648843 B 20190121
DOCDB simple family (application)
US 2013030874 W 20130313; CN 201380016755 A 20130313; CN 201810961862 A 20130313; EP 13767491 A 20130313; EP 16167775 A 20130313; EP 21160971 A 20130313; JP 2015503273 A 20130313; KR 20147024998 A 20130313; KR 20197018901 A 20130313; TW 102110014 A 20130321; TW 106126452 A 20130321