EP 3367374 A1 20180829 - AN ACTIVE MATRIX DISPLAY AND A METHOD FOR THRESHOLD VOLTAGE COMPENSATION IN AN ACTIVE MATRIX DISPLAY
Title (en)
AN ACTIVE MATRIX DISPLAY AND A METHOD FOR THRESHOLD VOLTAGE COMPENSATION IN AN ACTIVE MATRIX DISPLAY
Title (de)
AKTIVMATRIXANZEIGE UND VERFAHREN ZUR KONPENSIERUNG VON SCHWELLENSPANNUNG
Title (fr)
ECRAN A MATRICE ACTIVE PROCÉDÉ DE COMPENSATION POUR TENSION DE SEUIL
Publication
Application
Priority
EP 17158476 A 20170228
Abstract (en)
A method for threshold voltage compensation in an active matrix display (200) is provided. The display (200) comprises pixels (100), each comprising a drive transistor (102) having a driver gate (104) and a calibration gate (106), a first dataline (110) selectively connected to the driver gate (104), a second dataline (114) selectively connected to the calibration gate (106). The method comprises: driving (402) the display (200) in a calibration measurement mode for measuring a threshold voltage of a pixel (100), wherein the first dataline (110) is connected to the driver gate (104) and the second dataline (114) is connected to the calibration gate (106), and a measurement signal is actively driven to one of the first and the second dataline (110; 114) and a calibration signal is measured on the other of the first and the second dataline (110; 114), determining (404) calibration data based on the measured calibration signal; and driving (406) the display (200) in a calibration refresh mode, wherein the second dataline (114) is connected to the calibration gate (106) of the drive transistor (102), and the determined calibration data is provided on the second dataline (114) to the calibration gate (106) of the drive transistor (102).
IPC 8 full level
G09G 3/3275 (2016.01)
CPC (source: CN EP KR)
G09G 3/3225 (2013.01 - CN KR); G09G 3/3233 (2013.01 - EP); G09G 3/3275 (2013.01 - EP); G09G 2300/043 (2013.01 - EP KR); G09G 2300/0819 (2013.01 - EP); G09G 2300/0828 (2013.01 - KR); G09G 2300/0852 (2013.01 - EP); G09G 2310/0264 (2013.01 - CN); G09G 2320/0204 (2013.01 - EP); G09G 2320/0233 (2013.01 - EP); G09G 2320/0295 (2013.01 - EP); G09G 2320/045 (2013.01 - EP)
Citation (applicant)
- WO 02067327 A2 20020829 - IGNIS INNOVATION INC [CA], et al
- C. JEON ET AL.: "AMOLED Pixel Circuit using Dual Gate a-IGZO TFTs for Simple Scheme and High Speed V Extraction", SOCIETY FOR INFORMATION DISPLAY DIGEST, vol. 47, no. 1, 2016, pages 65 - 68
- BHOOLOKAM ET AL.: "Analysis of frequency dispersion in amorphous In-Ga-Zn-O thin-film transistors", JOURNAL OF INFORMATION DISPLAY, vol. 16, no. 1, 2015, pages 31 - 36
Citation (search report)
- [XA] US 2015317951 A1 20151105 - GENOE JAN [BE]
- [IA] US 2015236687 A1 20150820 - SHIMADA YUKIMINE [JP], et al
- [A] US 2013063413 A1 20130314 - MIYAKE HIROYUKI [JP]
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
DOCDB simple family (publication)
EP 3367374 A1 20180829; CN 108510942 A 20180907; CN 108510942 B 20220222; JP 2018141955 A 20180913; KR 20180099460 A 20180905; TW 201837891 A 20181016; TW I758410 B 20220321
DOCDB simple family (application)
EP 17158476 A 20170228; CN 201810168205 A 20180228; JP 2018001315 A 20180109; KR 20180006206 A 20180117; TW 107105026 A 20180212