EP 3704595 A4 20211222 - SYSTEM HAVING A HYBRID THREADING PROCESSOR, A HYBRID THREADING FABRIC HAVING CONFIGURABLE COMPUTING ELEMENTS, AND A HYBRID INTERCONNECTION NETWORK
Title (en)
SYSTEM HAVING A HYBRID THREADING PROCESSOR, A HYBRID THREADING FABRIC HAVING CONFIGURABLE COMPUTING ELEMENTS, AND A HYBRID INTERCONNECTION NETWORK
Title (de)
SYSTEM MIT EINEM HYBRIDEN THREADING-PROZESSOR, HYBRIDE THREADING-MATRIX MIT KONFIGURIERBAREN RECHENELEMENTEN UND HYBRIDES VERBINDUNGSNETZWERK
Title (fr)
SYSTÈME COMPRENANT UN PROCESSEUR DE SEGMENTATION HYBRIDE, MATRICE DE SEGMENTATION HYBRIDE COMPRENANT DES ÉLÉMENTS INFORMATIQUES CONFIGURABLES ET RÉSEAU D'INTERCONNEXION HYBRIDE
Publication
Application
Priority
- US 201762579749 P 20171031
- US 201862651134 P 20180331
- US 201862651131 P 20180331
- US 201862651132 P 20180331
- US 201862651128 P 20180331
- US 201862651142 P 20180331
- US 201862651140 P 20180331
- US 201862651135 P 20180331
- US 201862651137 P 20180331
- US 201862667679 P 20180507
- US 201862667792 P 20180507
- US 201862667749 P 20180507
- US 201862667850 P 20180507
- US 201862667717 P 20180507
- US 201862667780 P 20180507
- US 201862667760 P 20180507
- US 201862667666 P 20180507
- US 201862667691 P 20180507
- US 201862667820 P 20180507
- US 201862667699 P 20180507
- US 2018058539 W 20181031
Abstract (en)
[origin: CN111602126A] Representative apparatus, method, and system embodiments are disclosed for configurable computing. In a representative embodiment, a system includes: a first, interconnection network; a processor coupled to the interconnection network; a host interface coupled to the interconnection network; and at least one configurable circuit cluster coupled to the interconnection network, the configurable circuit cluster including: a plurality of configurable circuits arranged in an array; a second, asynchronous packet network coupled to each configurable circuit of the plurality of configurable circuits of the array; a third, synchronous network coupled to each configurable circuit of the plurality of configurable circuits of the array; a memory interface circuit coupled to the asynchronous packet network and to the interconnection network; and a dispatch interface circuit coupled to the asynchronous packet network and to the interconnection network.
IPC 8 full level
G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 13/16 (2006.01); G06F 13/40 (2006.01); G06F 15/78 (2006.01)
CPC (source: EP)
G06F 13/1684 (2013.01); G06F 13/4022 (2013.01); G06F 13/4027 (2013.01); G06F 15/7825 (2013.01); G06F 15/7867 (2013.01)
Citation (search report)
- [I] US 2013138913 A1 20130530 - BOX BRIAN A [US], et al
- [YA] US 2006150184 A1 20060706 - HANKINS RICHARD A [US], et al
- [XAY] EUSTACE PAINKRAS ET AL: "SpiNNaker: A 1-W 18-Core System-on-Chip for Massively-Parallel Neural Network Simulation", IEEE JOURNAL OF SOLID-STATE CIRCUITS, IEEE, USA, vol. 48, no. 8, 2 August 2013 (2013-08-02), pages 1943 - 1953, XP011520795, ISSN: 0018-9200, DOI: 10.1109/JSSC.2013.2259038
- [A] MELLETTE WILLIAM MAXWELL ET AL: "A Scalable, Partially Configurable Optical Switch for Data Center Networks", JOURNAL OF LIGHTWAVE TECHNOLOGY, IEEE, USA, vol. 35, no. 2, 15 January 2017 (2017-01-15), pages 136 - 144, XP011641222, ISSN: 0733-8724, [retrieved on 20170213], DOI: 10.1109/JLT.2016.2636025
- [A] ZHANG TAO TAO ZHANG@SJTU EDU CN ET AL: "Buddy SM", ACM TRANSACTIONS ON ARCHITECTURE AND CODE OPTIMIZATION, ASSOCIATION FOR COMPUTING MACHINERY, US, vol. 12, no. 2, 11 May 2015 (2015-05-11), pages 1 - 23, XP058493527, ISSN: 1544-3566, DOI: 10.1145/2744202
- See references of WO 2019089816A2
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
DOCDB simple family (publication)
CN 111602126 A 20200828; EP 3704595 A2 20200909; EP 3704595 A4 20211222
DOCDB simple family (application)
CN 201880070353 A 20181031; EP 18874782 A 20181031