EP 3782036 A1 20210224 - MIMD PROCESSOR EMULATED ON SIMD ARCHITECTURE
Title (en)
MIMD PROCESSOR EMULATED ON SIMD ARCHITECTURE
Title (de)
AUF SIMD-ARCHITEKTUR EMULIERTER MIMD-PROZESSOR
Title (fr)
PROCESSEUR MIMD ÉMULÉ SUR ARCHITECTURE SIMD
Publication
Application
Priority
- FR 1855012 A 20180608
- FR 2019051352 W 20190606
Abstract (en)
[origin: WO2019234359A1] The present invention relates to a processor having a SIMD architecture, comprising an array (120) of elementary processors (150), each elementary processor (150) being associated with an elementary memory cell (155), a central controller (110) connected to the elementary processors by an instruction bus and a status bus. The central controller transmits a sequence of instructions in a loop, each instruction comprising a calculation flow indicator. Each elementary processor has an instruction filter that makes it possible to reject or take into account an instruction depending on the identifier it contains. This operating mode makes it possible to emulate a MIMD processor on a SIMD architecture.
IPC 8 full level
G06F 15/80 (2006.01)
CPC (source: EP US)
G06F 5/06 (2013.01 - US); G06F 9/30101 (2013.01 - US); G06F 9/321 (2013.01 - US); G06F 9/3887 (2013.01 - EP US); G06F 15/80 (2013.01 - EP); G06F 15/8007 (2013.01 - US)
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
DOCDB simple family (publication)
WO 2019234359 A1 20191212; EP 3782036 A1 20210224; FR 3082331 A1 20191213; FR 3082331 B1 20200918; US 11182170 B2 20211123; US 2021240482 A1 20210805
DOCDB simple family (application)
FR 2019051352 W 20190606; EP 19742845 A 20190606; FR 1855012 A 20180608; US 201915734729 A 20190606