EP 3814923 A1 20210505 - ASYNCHRONOUS PROCESSOR ARCHITECTURE
Title (en)
ASYNCHRONOUS PROCESSOR ARCHITECTURE
Title (de)
ARCHITEKTUR EINES ASYNCHRONEN PROZESSORS
Title (fr)
ARCHITECTURE DE PROCESSEUR ASYNCHRONE
Publication
Application
Priority
- FR 1856000 A 20180629
- FR 2019051156 W 20190521
Abstract (en)
[origin: WO2020002783A1] The invention concerns a data processing method comprising: - a control unit, at least one ALU (9), a set of registers (11), a memory (13) and a memory interface (15). The method comprises: a) obtaining (101, 102) the memory addresses of the operands; b) reading (103, 104) the operands in the memory (13); c) transmitting (105) an instruction to execute calculations to the ALU (9) without an addressing instruction; d) executing all the elementary operations (106) by the ALU (9) receiving as input each of the operands from the registers (11); e) storing (107) the data forming results of the processing operation on the registers (11); f) obtaining (108) a memory address for each of the data items forming a result of the processing operation; g) writing (109) the results in the memory (13), for storage and via the memory interface (15), by means of the obtained memory addresses.
IPC 8 full level
G06F 15/80 (2006.01); G06F 9/38 (2018.01)
CPC (source: EP KR US)
G06F 9/34 (2013.01 - US); G06F 9/3885 (2013.01 - EP KR US); G06F 15/8015 (2013.01 - EP KR)
Citation (search report)
See references of WO 2020002783A1
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
DOCDB simple family (publication)
WO 2020002783 A1 20200102; CN 112639760 A 20210409; EP 3814923 A1 20210505; FR 3083351 A1 20200103; FR 3083351 B1 20210101; KR 20210021588 A 20210226; US 2021141644 A1 20210513
DOCDB simple family (application)
FR 2019051156 W 20190521; CN 201980055999 A 20190521; EP 19737810 A 20190521; FR 1856000 A 20180629; KR 20217002975 A 20190521; US 201917255791 A 20190521