EP 4042277 A1 20220817 - METHOD FOR REPRODUCIBLE PARALLEL SIMULATION AT ELECTRONIC SYSTEM LEVEL IMPLEMENTED BY MEANS OF A MULTI-CORE DISCRETE-EVENT SIMULATION COMPUTER SYSTEM
Title (en)
METHOD FOR REPRODUCIBLE PARALLEL SIMULATION AT ELECTRONIC SYSTEM LEVEL IMPLEMENTED BY MEANS OF A MULTI-CORE DISCRETE-EVENT SIMULATION COMPUTER SYSTEM
Title (de)
VERFAHREN ZUR REPRODUZIERBAREN PARALLELSIMULATION AUF ELEKTRONISCHER SYSTEMEBENE, DIE MITTELS EINES MULTICORE-SIMULATIONSRECHNERSYSTEMS MIT EREIGNISORIENTIERTER SIMULATION IMPLEMENTIERT IST
Title (fr)
PROCÉDÉ DE SIMULATION PARALLÈLE REPRODUCTIBLE DE NIVEAU SYSTÈME ÉLECTRONIQUE MIS EN OEUVRE AU MOYEN D'UN SYSTÈME INFORMATIQUE MULTI-COEURS DE SIMULATION À ÉVÉNEMENTS DISCRETS
Publication
Application
Priority
- FR 1911332 A 20191011
- EP 2020078339 W 20201008
Abstract (en)
[origin: WO2021069626A1] Disclosed is a method for reproducible parallel discrete event simulation at electronic system level implemented by means of a multi-core computer system, the simulation method comprising a series of evaluation phases, implemented by a simulation kernel executed by the computer system, comprising the following steps: - parallel process scheduling (1); - dynamic detection of shared addresses (2) of at least one shared memory of a simulated electronic system by concurrent processes, at addresses of the shared memory, using a state machine, respectively associated with each address of the shared memory; - avoidance of conflicts of access (3) to addresses of the shared memory by concurrent processes, by preemption of a process by the kernel when the process introduces an inter-process dependency of the "read-after-write" or "write-after-read-or-write" type; - verification of conflicts of access (4) to shared memory addresses by analysis of the inter-process dependencies using a trace of the accesses to the shared memory addresses of each evaluation phase and a search for cycles in an inter-process dependency graph; - backtracking (5), when at least one conflict is detected, to restore a past state of the simulation after determination of an order of conflict-free execution of the processes of the conflictual evaluation phase during which the conflict is detected, during a new simulation that is identical until the excluded conflictual evaluation phase is reached; and - generation of an execution trace (6) allowing the subsequent reproduction of the simulation in an identical manner.
IPC 8 full level
G06F 9/48 (2006.01); G06F 9/52 (2006.01); G06F 11/28 (2006.01)
CPC (source: EP US)
G06F 9/3877 (2013.01 - US); G06F 9/4881 (2013.01 - EP); G06F 9/4887 (2013.01 - US); G06F 9/52 (2013.01 - US); G06F 9/524 (2013.01 - EP); G06F 11/28 (2013.01 - EP)
Citation (search report)
See references of WO 2021069626A1
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
DOCDB simple family (publication)
FR 3101987 A1 20210416; FR 3101987 B1 20211001; EP 4042277 A1 20220817; US 2023342198 A1 20231026; WO 2021069626 A1 20210415
DOCDB simple family (application)
FR 1911332 A 20191011; EP 2020078339 W 20201008; EP 20786583 A 20201008; US 202017767908 A 20201008