EP 4275113 A1 20231115 - NUMERICAL PRECISION IN DIGITAL MULTIPLIER CIRCUITRY
Title (en)
NUMERICAL PRECISION IN DIGITAL MULTIPLIER CIRCUITRY
Title (de)
NUMERISCHE PRÄZISION IN DIGITALEN MULTIPLIZIERSCHALTUNGEN
Title (fr)
PRÉCISION NUMÉRIQUE DANS UN ENSEMBLE CIRCUIT MULTIPLICATEUR NUMÉRIQUE
Publication
Application
Priority
- US 202163134941 P 20210107
- US 2021039440 W 20210628
Abstract (en)
[origin: WO2022150058A1] In one embodiment, multiplier circuitry multiplies operands of a first format. One or more storage register circuits store digital bits corresponding to an operand and another operand of the first format. A decomposing circuit decomposes the operand into a first plurality of operands, and the other operand into a second plurality of operands. Each multiplier circuit multiplies a respective first operand of the first plurality of operands with a respective second operand of the second plurality of operands to generate a corresponding partial result of a plurality of partial results. An accumulator circuit accumulates the plurality of partial results using a second format to generate a complete result of the second format that is stored in the accumulator circuit. A conversion circuit truncates the complete result of the second format and converts the truncated result into an output result of an output format.
IPC 8 full level
G06F 7/544 (2006.01); G06F 5/08 (2006.01); G06F 7/498 (2006.01); G06F 7/527 (2006.01)
CPC (source: EP KR)
G06F 7/4876 (2013.01 - EP KR); G06F 7/5443 (2013.01 - EP KR); G06N 3/063 (2013.01 - KR)
Designated contracting state (EPC)
AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Designated extension state (EPC)
BA ME
Designated validation state (EPC)
KH MA MD TN
DOCDB simple family (publication)
WO 2022150058 A1 20220714; EP 4275113 A1 20231115; KR 20230121151 A 20230817
DOCDB simple family (application)
US 2021039440 W 20210628; EP 21918010 A 20210628; KR 20237025858 A 20210628